Through Package Vertical Interconnect and Method of Making Same

ABSTRACT

In integrated circuit packages, a coaxial pair of signals are routed through a plated through hole between circuitry on one face of the core substrate material with circuitry on an opposing face of the core substrate material. Provided are methods and apparatuses where signals are routed within a concentric reference conductor within traditional package substrates. Methods for forming a hole in the core substrate material through which the coaxial pair of signals is passed on a fine pitch.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to the following:

-   -   1. Provisional Application Ser. No. 63/334,449, filed 25 Apr.        2022 (“Parent Provisional”).

This application claims priority to the Parent Provisional, and herebyclaims benefit of the filing date thereof pursuant to 37 C.F.R. §1.78(a).

The subject matter of the Parent Provisional in its entirety isexpressly incorporated herein by reference.

BACKGROUND Field of Invention

Embodiments of the present invention are directed to semiconductorpackaging and, more particularly, to improve performance and reduce areaby utilizing a coaxial approach where signals are routed within aconcentric reference conductor within traditional package substrates.

Description of Related Art

Integrated circuit (“IC”) substrate or IC package substrate may be abasic material used in advanced packaging applications used to packagebare IC chips. IC substrate may act as the connection between IC chipand PCB through a conductive network of wires and holes. IC packagingsubstrate has been developed over the years on the basis of HigherDensity Interconnect (“HDI”)/Built Up Multilayer (“BUM”) board; ICpackaging substrate is HDI/BUM board with higher densities. An ICsubstrate may be a pattern of conductors that corresponds to the wiringof an electronic circuit formed on one or more layers of insulativematerial. The IC substrate includes electrical traces that are routed onor through the various layers of the substrate. IC substrate alsoinclude through package vertical interconnect or plated through holes(“PTH”) which are solid electrical paths connecting one layer to anotherlayer. Traditionally, package substrates use PTH to conduct I/O signalsor voltage supply through the substrate core. However, the performanceand area occupied by the PTHs is largely determined by the PTH-PTHpitch. This also impacts the ground separation.

What is needed is an improved method and apparatus for use insemiconductor packaging substrates, and in particular to improve theperformance and reduce the area utilized by PTHs in semiconductorpackaging substrates by utilizing a coaxial approach where signals arerouted within a concentric reference conductor within traditionalpackage substrates. In particular, we submit that such a method andapparatus should provide performance generally comparable to the bestprior art techniques but more efficiently than known implementations ofsuch prior art techniques.

SUMMARY OF THE INVENTION

According to one embodiment, a method of forming a coaxial structure,the coaxial structure comprising a concentric reference structure and afirst and second through-via formed therein, in an insulativesemiconductor substrate core, the method comprising the steps of:forming a hole in the insulative semiconductor substrate core, the holehaving an inner surface from a first side of the insulativesemiconductor substrate core to a second side of the insulativesemiconductor substrate core; depositing over the inner surface of thehole in the insulative semiconductor substrate a conductive material toform the concentric reference structure from the first side of theinsulative semiconductor substrate core to the second side of theinsulative semiconductor substrate core through the hole; depositing afirst dielectric material in the hole; depositing a second dielectricmaterial on the surface of the first and second sides of the insulativesemiconductor substrate core; forming the first and second through-viathrough the second dielectric material on the first and second sides ofthe insulative semiconductor substrate core and within the firstdielectric material in the hole.

According to a different embodiment, a method for forming a coaxialstructure, the coaxial structure comprising a concentric referencestructure and a first and second through via formed therein, in aconductive semiconductor substrate core, the method comprising the stepsof: forming a first hole in the conductive semiconductor substrate core,the first hole having an inner surface from a first side of theconductive semiconductor substrate core to a second side of theconductive semiconductor substrate core; depositing a first dielectricmaterial in the first hole; forming a second hole within the dielectricmaterial deposited in the first hole; depositing over the inner surfaceof the second hole in the conductive semiconductor substrate aconductive material to form the concentric reference structure from thefirst side of the conductive semiconductor substrate core to the secondside of the conductive semiconductor substrate core through the secondhole; depositing a second dielectric material in the second hole;forming a first and second through vias within the second dielectricmaterial in the second hole.

According to a yet a different embodiment, a packaging substrate corecomprising: a substrate comprising: a first surface; a cavity formedinto the first surface to a depth less than the thickness of theinsulating substrate; an active component disposed the cavity; and avertical interconnect module disposed within the cavity.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 illustrates, in diagrammatic form, a cut-away side view and atop-down view of a fabrication process of an insulating semiconductorsubstrate core having a coaxial structure that includes a concentricreference structure and a pair of signal PTH formed therein, inaccordance with at least one embodiment;

FIG. 2A illustrates, in flow chart form, a fabrication process of aninsulating semiconductor substrate core having a coaxial structure thatincludes a concentric reference structure and a pair of signal PTHformed therein, in accordance with at least one embodiment;

FIG. 2B illustrates, in flow chart form, another fabrication process ofan insulating semiconductor substrate core having a coaxial structurethat includes a concentric reference structure and a pair of signal PTHformed therein, in accordance with at least one embodiment;

FIG. 3 illustrates, in diagram form, a cut-away side view of afabrication process of a conductive semiconductor substrate core havinga coaxial structure that includes a concentric reference structure and apair of signal PTH formed therein, in accordance with at least oneembodiment;

FIG. 4A illustrates, in flow chart form, a fabrication process of aconductive semiconductor substrate core having a coaxial structure thatincludes a concentric reference structure and a pair of signal PTHformed therein, in accordance with at least one embodiment;

FIG. 4B illustrates, in flow chart form, another fabrication process ofa conductive semiconductor substrate core having a coaxial structurethat includes a concentric reference structure and a pair of signal PTHformed therein, in accordance with at least one embodiment;

FIG. 5 illustrates, in diagram form, a cut-away side view of afabrication process of a conductive semiconductor substrate coaxialstructure that includes a concentric reference structure and a pair ofsignal PTH formed therein with the conductive core as the reference, inaccordance with at least one embodiment;

FIG. 6 illustrates, in flow chart form, a fabrication process of aconductive semiconductor substrate coaxial structure that includes aconcentric reference structure and a pair of signal PTH formed thereinwith the conductive core as the reference, in accordance with at leastone embodiment;

FIG. 7 illustrates, in diagram form a top view of a semiconductorsubstrate core having a cavity having a PTH rectangular region formedtherein, in accordance with at least one embodiment;

FIG. 8 illustrates, in diagram form, a top view of a semiconductorsubstrate core having a cavity having a PTH alley region formed therein,in accordance with at least one embodiment;

FIG. 9 illustrates, in diagram form, a vertical interconnect module foruse in a semiconductors substrate core having a PTH region formedtherein, in accordance with at least one embodiment;

FIG. 10 illustrates, in diagram form, a conductive slug module for usein a semiconductors substrate core having a conductive slug regionformed therein, in accordance with at least one embodiment;

FIG. 11 illustrates, in diagram form, a semiconductor substrate corehaving a cavity including a vertical interconnect module and aconductive slug module utilized therein, in accordance with at least oneembodiment;

FIG. 12 illustrates, in diagrammatic form, a cut-away side view of atraditional package substrate with die mounted atop the substrate, ballconnectors on the bottom of the substrate, and devices embedded withinthe core of the substrate; and

FIG. 13 illustrates, in diagrammatic form, a cut-away side view of apackage substrate with die mounted atop the substrate, ball connectorson the bottom of the substrate, and adapted to utilize at least avertical interconnect module or a conductive slug module, in accordancewith at least one embodiment.

DETAILED DESCRIPTION

Reference throughout this specification to “one embodiment” or “anembodiment” means that a particular feature, structure, orcharacteristic described in connection with the embodiment is includedin at least one embodiment of the present invention. Thus, theappearances of the phrases “in one embodiment” or “in an embodiment” invarious places throughout this specification are not necessarily allreferring to the same embodiment. Furthermore, the particular features,structures, or characteristics may be combined in any suitable manner inone or more embodiments.

Traditional package substrates use single plated through holes (PTHs) toconduct IO signals or voltage supply through the substrate core. Theperformance and area occupied by these PTHs is largely determined by thePTH-PTH pitch (which also determines the ground separation). Inaccordance with at least one embodiment, the structure improvesperformance and reduces area by utilizing a coaxial approach wheresignals are routed within a concentric reference conductor. The coaxstructure could be formed in same layer, or in 2 different layers. PTHmay be fully or partially filled. The PTH hole fill material can be thesame or different material than the buildup material. The core could beinsulating or conducting (where the conductive core could be used asreference conductor).

FIG. 1 illustrates, in diagrammatic form, a cut-away side view and atop-down view of a fabrication process of an insulating semiconductorsubstrate core having a coaxial structure that includes a concentricreference structure and a pair of signal through vias, i.e., PTHs,formed therein, in accordance with at least one embodiment. In FIG. 1 ,a hole 104 is formed in the insulating substrate core 102. Formation ofthe hole 104 may take place through the use of a device which mayinclude a mechanical means, such as a mechanical drill, or anelectromagnetic device, such as a laser for ablating substrate material.The hole 104 through the insulating substrate core 102 may be furtherformed by way of a chemical etching process, such as a plasma etchingprocess, the specifics of which are appreciated by those of ordinaryskill in the art and are not further described herein. The hole 104 hasan inner surface spanning from one side of the insulating substrate core102 to the opposite side of the insulating substrate core 102. Asfurther illustrated in FIG. 1 , following the formation of the hole 104in the insulating substrate core 102, a concentric reference structure106 is formed using conductive material within the hole 104, thespecifics of which are appreciated by those of ordinary skill in theart. The conductive material may be deposited using industry standardtechniques such as physical vapor deposition (“PVD”), also known assputtering, electrochemical deposition (“ECD”), conductive ink-filltechniques for metals, and similar well understood techniques such aselectro plating. The concentric reference structure 106 is deposited onthe inner surface of the hole 104, covering the inner surface of thehole 104 from one side of the insulating substrate core 102 to theopposite side of the insulating substrate core 102.

Further illustrated in FIG. 1 , a dielectric material 108 is used tofill the hole 104 containing the concentric reference structure 106.Dielectric material 108 is typically a material having a lowpermittivity that is more easily drilled through laser drilling methodsthan materials such as glass fiber reinforced epoxy resins and isdeposited in the hole using standard packaging techniques, such as forexample, squeegee printing or stencil printing with squeegee. The upperand lower surfaces of the insulating substrate core 102 are alsolaminated using a dielectric or insulative material. This dielectric orinsulative material may be the same as the dielectric material 108 usedto fill hole 104, or it may be of a different composition. Thisdielectric or insulative material is illustrated in FIG. 1 as dielectriclaminate 110. FIG. 1 also illustrates, a pair of holes are then formedthrough the dielectric laminate 110 and through the dielectric material108 used to fill hole 104 using processes well understood such asmechanical drilling processes or laser drilling processes, depending onthe dimensions of the hole to be created. The second pair of holes areco-axially aligned with the hole 104 and with each other. Conductivematerial is deposited in the pair of holes, forming a first and secondthrough via and having been formed co-axially aligned with hole 104through the dielectric laminate 110 and the dielectric material 108 usedto fill hole 104, and capped with the same conductive material to formthe PTH 112. Capping typically is done as part of a patterning process.Conducting materials include metals such as copper, aluminum, andtungsten. The conducting material may be deposited, by way of example,in the hole for PTH 112 by PVD, ECD, or electrical plating, for example.

FIG. 1 also illustrates, in diagrammatic form, a cut-away side view anda top-down view of a fabrication process of an insulating semiconductorsubstrate core having a coaxial structure that includes a concentricreference structure and a pair of signal through vias, i.e., PTHs,formed therein, in accordance with at least one embodiment. In FIG. 1 ,a hole 104′ is formed in the insulating substrate core 102. Formation ofthe hole 104′ may take place through the use of a device which mayinclude a mechanical means, such as a mechanical drill, or anelectromagnetic device, such as a laser for ablating substrate material.The hole 104′ through the insulating substrate core 102 may be furtherformed by way of a chemical etching process, such as a plasma etchingprocess, the specifics of which are appreciated by those of ordinaryskill in the art and are not further described herein. The hole 104′ hasan inner surface spanning from one side of the insulating substrate core102 to the opposite side of the insulating substrate core 102. Asfurther illustrated in FIG. 1 , following the formation of the hole 104′in the insulating substrate core 102, a dielectric material 108 is usedto fill the hole 104′. Dielectric material 108 is typically a materialhaving a low permittivity that is more easily drilled through laserdrilling methods than materials such as glass fiber reinforced epoxyresins and is deposited in the hole using standard packaging techniques,such as for example, squeegee printing or stencil printing withsqueegee. The upper and lower surfaces of the insulating substrate core102 are also laminated using a dielectric or insulative material. Thisdielectric or insulative material may be the same as the dielectricmaterial 108 used to fill hole 104′, or it may be of a differentcomposition. This dielectric or insulative material is illustrated inFIG. 1 as dielectric laminate 110.

Following the deposition of the dielectric material 108 into hole 104′and the deposition of the dielectric laminate 110, the concentricreference structure 114 is created by forming the ring, doughnut,semicircle, or holes through the dielectric laminate 110 and through thedielectric material 108 used to fill hole 104′. The concentric referencestructure is by depositing conductive material within the ring, etc.,industry standard techniques such as physical vapor deposition (“PVD”),also known as sputtering, electrochemical deposition (“ECD”), conductiveink-fill techniques for metals, and similar well understood techniquessuch as electro plating. Subsequent to forming the concentric referencestructure 114, FIG. 1 also illustrates, a pair of holes are then formedthrough the dielectric laminate 110 and through the dielectric material108 used to fill hole 104′ using processes well understood such asmechanical drilling processes or laser drilling processes, depending onthe dimensions of the hole to be created. The second pair of holes areco-axially aligned with the hole 104′ and the concentric referencestructure 114, as well as with each other. Conductive material isdeposited in the pair of holes having been formed co-axially alignedwith hole 104′ through the dielectric laminate 110 and the dielectricmaterial 108 used to fill hole 104′, and capped with the same conductivematerial to form the through vias, i.e., PTHs 112. Capping typically isdone as part of a patterning process. Conducting materials includemetals such as copper, aluminum, and tungsten. The conducting materialmay be deposited, by way of example, in the hole for PTH 112 by PVD,ECD, or electrical plating, for example.

FIG. 2A illustrates, in flow chart form, a fabrication process 200 of aninsulating semiconductor substrate core having a a coaxial structurethat includes a concentric reference structure and a pair of signalthrough vias, i.e., PTHs, formed therein, in accordance with at leastone embodiment. In FIG. 2A, box 202, a insulative semiconductorsubstrate core is provided and one or more holes are formed through theinsulative semiconductor substrate core. A conductive material is thendeposited over the inside surface of the hole or holes forming theconcentric reference structure on the inside surface of the hole orholes (box 204). A dielectric material is then deposited into the platedhole (box 206). A dielectric material is next deposited on the surfacesof the insulative semiconductor substrate core (box 208). A pair ofcoaxially aligned holes are then formed through the dielectric plug.Metal is deposited into the holes using industry standard techniquessuch as PVD and ECD techniques for metals, and a coaxial pair of throughvias, i.e., PTHs, is thus formed within the dielectric plug in the hole(box 210).

FIG. 2B illustrates, in flow chart form, a fabrication process 212 of aninsulating semiconductor substrate core having a a coaxial structurethat includes a concentric reference structure and a pair of signalthrough vias, i.e., PTH formed therein, in accordance with at least oneembodiment. In FIG. 2B, box 214, an insulative semiconductor substratecore is provided and one or more holes are formed through the insulativesemiconductor substrate core. A dielectric material is then depositedinto the hole (box 216). A dielectric material is next deposited on thesurfaces of the insulative semiconductor substrate core (box 218). Aconcentric reference structure is then formed through the dielectricmaterial deposited in the hold (box 220). A pair of coaxially alignedholes are then formed through the dielectric plug. Metal is depositedinto these holes forming the through vias, or PTHs, using industrystandard techniques discussed above (box 222).

FIG. 3 illustrates, in diagram form, a cut-away side view of afabrication process of a conductive semiconductor substrate core havinga coaxial structure that includes a concentric reference structure and apair of signal PTH formed therein, in accordance with at least oneembodiment. In FIG. 3 , one or more hole(s) 304 is formed in theconductive semiconductor substrate core 302. The hole 304 has an innersurface spanning from one side of the conductive semiconductor substratecore 302 to the opposite side of the conductive semiconductor substratecore 302. Dielectric material 306 is then deposited both in the hole 304and on the surface of the conductive semiconductor substrate core 302. Ahole is then formed through the dielectric material 306 deposited inhole 304 and a conductive material 308 is formed within the hole formedthrough the dielectric material 306 deposited in hole 304, forming theconcentric reference structure. The conductive material 308 is depositedsuch that it does not contact the conductive semiconductor substratecore 302.

Further illustrated in FIG. 3 , a dielectric material 310 is used tofill the PTH hole. Dielectric material 310 is typically a materialhaving a low permittivity that is more easily drilled through laserdrilling methods than materials such as glass fiber reinforced epoxyresins and is deposited in the hole using standard semiconductorpackaging techniques, such as for example, squeegee printing or stencilprinting with squeegee. This dielectric or insulative material may bethe same as the dielectric material 306 used to deposit on the surfacesof the conductive semiconductor substrate core 302 as well as initiallydeposited in the hole 304, or it may be of a different composition. FIG.3 also illustrates, a pair of holes are then formed through thedielectric plug 310 using processes well understood such as mechanicaldrilling processes or laser drilling processes, depending on thedimensions of the hole to be created. The second pair of holes areco-axially aligned with the hole 304 and with each other. Conductivematerial is deposited in the pair of holes having been formed co-axiallyaligned with hole 304 through the dielectric plug 310, and capped withthe same conductive material to form the through vias, i.e., PTHs, 312.Capping typically is done as part of a patterning process. Conductingmaterials include metals such as copper, aluminum, and tungsten. Theconducting material may be deposited, by way of example, in the hole forPTH 112 by PVD, ECD, or electrical plating, for example.

FIG. 3 also illustrates, in diagrammatic form, a cut-away side view ofanother fabrication process of an insulating semiconductor substratecore having a coaxial structure that includes a concentric referencestructure and a pair of signal PTH formed therein, in accordance with atleast one embodiment. In FIG. 3 , one or more hole(s) 304 is formed inthe insulating substrate core 302. Formation of the hole 304 may takeplace through the use of a device which may include a mechanical means,such as a mechanical drill, or an electromagnetic device, such as alaser for ablating substrate material. The hole 304 through theinsulating substrate core 302 may be further formed by way of a chemicaletching process, such as a plasma etching process, the specifics ofwhich are appreciated by those of ordinary skill in the art and are notfurther described herein. The hole 304 has an inner surface spanningfrom one side of the insulating substrate core 302 to the opposite sideof the insulating substrate core 302. As further illustrated in FIG. 3 ,following the formation of the hole 304 in the insulating substrate core302, a dielectric material 306 is used to fill the hole 304. Dielectricmaterial 306 is typically a material having a low permittivity that ismore easily drilled through laser drilling methods than materials suchas glass fiber reinforced epoxy resins and is deposited in the holeusing standard packaging techniques, such as for example, squeegeeprinting or stencil printing with squeegee. The upper and lower surfacesof the insulating substrate core 302 are also laminated using adielectric or insulative material. This dielectric or insulativematerial may be the same as the dielectric material 306 used to fillhole 304, or it may be of a different composition.

Following the deposition of the dielectric material 306 into hole 304and on the surfaces of substrate core 302, the concentric referencestructure 308′ is created by forming the ring or holes through thedielectric material 306 used to fill the hole 304 and apply to thesurface of substrate core 302. Conductive material is deposited in theconcentric reference structure using processes well understood by thoseof ordinary skill in this art. Subsequent to forming the concentricreference structure 308′, FIG. 3 also illustrates, a pair of holes arethen formed through the dielectric material 306 used to fill the hole304 and disposed on the surface of substrate core 302 using processeswell understood such as mechanical drilling processes or laser drillingprocesses, depending on the dimensions of the hole to be created. Thesecond pair of holes are co-axially aligned with the hole 304 and theconcentric reference structure 308′, as well as with each other.Conductive material is deposited in the pair of holes having been formedco-axially aligned with hole 304′ through the dielectric material 306used to fill hole 304, and capped with the same conductive material toform the PTHs 312. Capping typically is done as part of a patterningprocess. Conducting materials include metals such as copper, aluminum,and tungsten. The conducting material may be deposited, by way ofexample, in the hole for PTH 312 by PVD, ECD, or electrical plating, forexample.

FIG. 4A illustrates, in flow chart form, a fabrication process 400 of aconductive semiconductor substrate core having a coaxial structure thatincludes a concentric reference structure and a pair of signal PTHformed therein, in accordance with at least one embodiment. In FIG. 4A,box 402, a conductive semiconductor substrate core is provided and oneor more holes are drilled through the insulative semiconductor substratecore. A dielectric material is deposited in the hole formed in theconductive semiconductor substrate core and on the surface of theconductive semiconductor substrate core (box 404). A hole is formed inthe dielectric material deposited in the hole formed in the conductivesemiconductor substrate core (box 406). A conductive material is thendeposited over the inside surface of the hole or holes (box 408) formingthe concentric reference structure. A dielectric plug is then depositedinto the hole having the conductive material deposited therein (box410). A pair of coaxially aligned holes are then formed through thedielectric plug. A conductive material is deposited into the holesformed in the dielectric plug using industry standard techniques such asPVD and ECD techniques for metals, and a coaxial pair of PTH is formedwithin the dielectric plug in the hole (box 412).

FIG. 4B illustrates, in flow chart form, a fabrication process 414 of aconductive semiconductor substrate core having a coaxial structure thatincludes a concentric reference structure and a pair of signal PTHformed therein, in accordance with at least one embodiment. In FIG. 4B,box 416, a conductive semiconductor substrate core is provided and oneor more holes are drilled through the insulative semiconductor substratecore. A dielectric material is deposited in the hole formed in theconductive semiconductor substrate core and on the surface of theconductive semiconductor substrate core (box 418). A hole is formed inthe dielectric material deposited in the hole formed in the conductivesemiconductor substrate core (box 406). The concentric referencestructure is next formed by boring or trenching holes in the dielectricmaterial placed in the hole (box 420). A pair of coaxially aligned holesare then formed through the dielectric plug. A conductive material isdeposited into the holes formed in the dielectric plug using industrystandard techniques such as PVD, ECD, and conductive ink-fill techniquesfor metals, and a coaxial pair of PTH is formed within the dielectricplug in the hole (box 422).

FIG. 5 illustrates, in diagram form, a cut-away side view of afabrication process of a conductive semiconductor substrate core havinga coaxial pair PTH formed therein with the conductive core as thereference, in accordance with at least one embodiment. In FIG. 5 , ahole 504 is formed in the conductive semiconductor substrate core 502.The hole 504 has an inner surface spanning from one side of theconductive semiconductor substrate core 502 to the opposite side of theconductive semiconductor substrate core 502. Dielectric material 506 isthen deposited both in the hole 504 and on the surface of the conductivesemiconductor substrate core 502. FIG. 5 also illustrates, a pair ofholes are then formed through the dielectric material deposited in hole504 using processes well understood such as mechanical drillingprocesses or laser drilling processes, depending on the dimensions ofthe hole to be created. The pair of holes are co-axially aligned withthe hole 504 and with each other. Conductive material is deposited inthe pair of holes having been formed co-axially aligned with hole 504through the dielectric material 506, and capped with the same conductivematerial to form the PTH 508. Capping typically is done as part of apatterning process. Caps are also formed to connect to the conductivesemiconductor substrate so that the conductive semiconductor substratecore may be utilized as the reference for the coaxial pair. Conductingmaterials include metals such as copper, aluminum, and tungsten. Theconducting material may be deposited, by way of example, in the hole forPTH 508 by PVD, ECD, or electrical plating, for example.

FIG. 6 illustrates, in flow chart form, a fabrication process of aconductive semiconductor substrate core having a coaxial pair PTH formedtherein, in accordance with at least one embodiment. In FIG. 6 , box602, a conductive semiconductor substrate core is provided and one ormore holes are drilled through the insulative semiconductor substratecore. A dielectric material is deposited in the hole formed in theconductive semiconductor substrate core and on the surface of theconductive semiconductor substrate core (box 604). A pair of coaxiallyaligned holes are then drilled through the dielectric material in theformed hole. Metal is deposited into the holes using industry standardtechniques such as PVD, ECD, conductive ink-fill techniques for metals,and a coaxial pair of PTH is formed within the dielectric plug in thehole (box 606).

Typically, package core substrates (e.g., thick package core substrates,such as laminate core substrates) are comprised of glass fiber or glasscloth filled epoxide. The typical thickness of the core substratesuseful in the present invention is 100 to 1200 μm, or 250 to 1000 μm.

Mechanical drilling to form holes in package substrates can beperformed, for example, using mechanical drill bits and by waterdrilling and sand blasting techniques. Laser drilling to form vias canbe performed, for example, using an excimer laser, an ultraviolet (UV)laser, or a CO₂ laser. More generally, any type of laser that issuitable for the process of via formation may be used to form vias.

In general, low permittivity materials are materials that do not containglass fiber or other materials that can cause laser diffraction.Exemplary low permittivity filler materials include epoxy resin filmpolyimide (PI), and epoxy resin with silicon filler available.

Conducting materials include, for example, metals such as copper andaluminum. Standard semiconductor techniques are employed to depositmetals in holes and form caps. For example, techniques such as PVD (alsoknown as sputtering), ECD, and electrical plating are employed.

Holes formed, do not necessarily have to be circular in shape whenviewed from above, they may also be elliptical, for example.Advantageously, embodiments of the present invention are not limited toholes having a particular shape.

Traditionally, PTHs are formed in the core of the package substrate. Inpackage and boards with devices embedded in the cavity formed in thesubstrate core, e.g., capacitors, inductors, active chips, etc.,traditional PTH will be required to remain outside of the cavity region.These PTHs can be grouped to form an island amidst embedded devices orbe formed as alleys or donuts under the PHY region of the surfacemounted chip. These PTHs can also be used to remove heat from hotspotsof the surface mounted/embedded device. These PTHs could also bepre-formed as modules and embedded along with the other devices, asfurther discussed below.

FIG. 7 illustrates, in diagram form a top view of a semiconductorsubstrate core 700 having a cavity having a PTH rectangular regionformed therein, in accordance with at least one embodiment.Semiconductor substrate core 700 includes a substrate core 702.Substrate core 702 includes a cavity 704 with embedded devices 706. Asdiscussed earlier, embedded devices may include capacitors, inductors,active semiconductor chips, and the like. PTH rectangular region 708allows for utilization of this region through the cavity to reduce theIO routing length and improve performance associated with shorterrouting distances.

FIG. 8 illustrates, in diagram form, a top view of a semiconductorsubstrate core 800 having a cavity having a PTH alley region formedtherein, in accordance with at least one embodiment. Semiconductorsubstrate core 800 includes a substrate core 802. Substrate core 802includes a cavity 804 with embedded devices 806. As discussed earlier,embedded devices may include capacitors, inductors, active semiconductorchips, and the like. PTH alley region 808 allows for utilization of thisregion through the cavity to reduce the IO routing length and improveperformance associated with shorter routing distances.

FIG. 9 illustrates, in diagram form, a vertical interconnect module 900for use in a semiconductors substrate core having a PTH region formedtherein, in accordance with at least one embodiment. Verticalinterconnect module 900 may be fabricated and pre-formed using any ofthe previously mentioned methods. Vertical interconnect module 900includes at least one vertical conductor or PTH 904 and will comprise aninsulative or dielectric material mold 902. Advantageously, thesepre-fabricated, pre-formed interconnect modules 900 may contain arraysof PTHs and be formed to fit into specific X, Y, and Z dimensions,depending on the need. These preformed modules may facilitateintegration of fat wires for lower resistance in comparison totraditional PTH that may be fully filled. Such prefab modules may alsoallow for finer pitch connections, especially in thicker cores.Traditionally, PTH diameter and pitch is limited by core thickness, highaspect ratio PTHs, and substrate manufacturing tolerances. These modulesmay include a pre-formed interconnect network as part of a conductiveframe prior to embedding, e.g., coaxial PTHs, etc. This may allow formaterials and structures that may not be compatible with substratemanufacturing flows.

FIG. 10 illustrates, in diagram form, a conductive slug module 1000 foruse in a semiconductors substrate core having a conductive slug regionformed therein, in accordance with at least one embodiment. Conductiveslug module 1000 may be fabricated and pre-formed using any of thepreviously mentioned methods. Conductive slug module 1000 includes atleast one conducting slug 1002 and will comprise an insulative ordielectric material mold 1004. Advantageously, these pre-fabricated,pre-formed interconnect modules 900 may contain arrays of PTHs and beformed to fit into specific X, Y, and Z dimensions, depending on theneed. Similar to vertical interconnect module 900, these preformedmodules may facilitate integration of fat wires for lower resistance incomparison to traditional PTH that may be fully filled. Such prefabmodules may also allow for finer pitch connections, especially inthicker cores. These modules may include a pre-formed interconnectnetwork as part of a conductive frame prior to embedding, e.g., coaxialPTHs, etc. This may allow for materials and structures that may not becompatible with substrate manufacturing flows. Conductive slug module1000 may be used in cases where fewer interconnects are required,further improving resistance. In each instance, there are exposed metalconnections points on multiple sides of the modules to facilitate viaconnects to packaging RDL.

FIG. 11 illustrates, in diagram form, a semiconductor substrate core1100 having a cavity including a vertical interconnect module and aconductive slug module utilized therein, in accordance with at least oneembodiment. Semiconductor substrate core 1100 includes a substrate core1102 and a substrate cavity 1104. Substrate cavity 1104 is adapted toinclude devices 1106 which may include devices such as such ascapacitors, capacitor modules, inductors, inductors modules, activedevices such as functional semiconductor chips, etc. FIG. 12illustrates, in diagrammatic form, a cut-away side view of a traditionalpackage substrate 1200 with die mounted atop the substrate, ballconnectors on the bottom of the substrate, and devices embedded withinthe core of the substrate. FIG. 12 illustrate a particular problem withthe traditional package or board with devices embedded in a cavity suchas the substrate cavity 1104 illustrated in FIG. 11 . Traditionally,PTHs are formed in the core of the package. For packages or boards withdevices embedded in a cavity formed in the substrate core, e.g.,capacitors, inductors, active chips, etc., traditional PTHs are requiredto remain outside of the cavity region. By way of example only, FIG. 12illustrates a substrate core 1202 with a cavity region containingdevices 1204. Connecting solder ball A to die input/output A′ which isabove the cavity region requires a route by way of PTH 1206. The pathillustrated by PTH 1206 adds additional interconnect length and theconcomitant capacitance, resistance, and signally penalties typicallyassociated with lengthier interconnect. Embodiments of the subjectmatter disclosed herein address this issue in at least three differentways.

First, PTH's may be provided in gapfill material traditionally used inthe cavity of a substrate core and illustrated herein in FIG. 7 and FIG.8 . These structures illustrate the use of PTH's through the cavityregion, which may be filled with an insulator, to reduce the signalrouting length and provide the concomitant performance improvements. Asillustrated, these PTHs may be formed in groups to form islands amidstembedded devices as illustrated in FIG. 7 , be formed as alleys under aarea with critical timing constraints such as a PHY interface for asurface mounted chip as illustrated in FIG. 8 , or be formed into othershapes such as donuts, half moons, and similar geometric shapes. PTYssuch as these illustrated in FIG. 7 and FIG. 8 may also be used toremove heat from hotspots of the surface mounted and/or embeddeddevices.

Secondly, the PTH's may be a pre-formed PTH module such as the verticalinterconnect module 900 illustrated in FIG. 9 , and may be picked,placed, and embedded in the cavity of a substrate core along with otherdevices. Forming vertical interconnect module 900 with various diameterPTHs provides for the use of ‘fat’ wires for facilitating interconnectwith lower resistance in comparison to traditional PTH which may not befully filled with conductive material. Such prefabricated modules mayalso provide for finer pitch connections, specifically in thickersubstrate cores. As is understood, traditionally, PTH diameter and pitchmay be limited by substrate core thickness, high aspect ratio PTHs, andsubstrate core manufacturing tolerances. Additionally, these modules mayinclude pre-formed interconnect network prior to embedding, i.e., aspart of a conductive frame such as Coaxial PTHs. This may facilitate theuse of materials and structures that may not be compatible withsubstrate manufacturing flows.

Third, the PTH's may be a preformed conductive slug module 1000illustrated in FIG. 10 , and again, may be picked, placed, and embeddedin the cavity of a substrate core along with other devices. Conductiveslug module 1000 may be used in situations where fewer interconnectionsare required to further improve resistance characteristics within thepackage, or to dissipate heat. In both instances, vertical interconnectmodule 900 and conductive slug module 1000 may be pre-fabricated withexposed metal on multiple sides of the respective modules to facilitatevia connections to package RDL.

FIG. 13 illustrates, in diagrammatic form, a cut-away side view of apackage substrate 1300 with die mounted atop the substrate, ballconnectors on the bottom of the substrate, and adapted to utilize atleast a vertical interconnect module 900 or a conductive slug module1000, in accordance with at least one embodiment. Package substrate core1300 includes substrate core 1302, device 1304, vertical interconnectmodule 1306, conductive slug module 1308, and vertical interconnectthrough the cavity fill material 1310, also illustrated in FIG. 8 , PTHalley region 808. As can illustrated, vertical interconnect module 1306provides for PTHs that are more directly connect solder ball A to dieinput/output A′ which is above the cavity region. Likewise, conductiveslug module 1308 provides for improved resistance when connecting solderball P to die input/output P′.

Thus, it will be apparent to one of ordinary skill that this disclosureprovides for improved method and apparatus for use in semiconductorpackaging substrates, and in particular to improve the performance andreduce the area utilized by PTHs in semiconductor packaging substratesby utilizing a coaxial approach where signals are routed within aconcentric reference conductor within traditional package substrates.

Apparatus, methods and systems according to embodiments of thedisclosure are described. Although specific embodiments are illustratedand described herein, it will be appreciated by those of ordinary skillin the art that any arrangement which is calculated to achieve the samepurposes can be substituted for the specific embodiments shown. Thisapplication is intended to cover any adaptations or variations of theembodiments and disclosure. For example, although described interminology and terms common to the field of art, exemplary embodiments,systems, methods and apparatus described herein, one of ordinary skillin the art will appreciate that implementations can be made for otherfields of art, systems, apparatus or methods that provide the requiredfunctions. The invention should therefore not be limited by theabove-described embodiment, method, and examples, but by all embodimentsand methods within the scope and spirit of the invention.

In particular, one of ordinary skill in the art will readily appreciatethat the names of the methods and apparatus are not intended to limitembodiments or the disclosure. Furthermore, additional methods, steps,and apparatus can be added to the components, functions can berearranged among the components, and new components to correspond tofuture enhancements and physical devices used in embodiments can beintroduced without departing from the scope of embodiments and thedisclosure. One of skill in the art will readily recognize thatembodiments are applicable to future systems, future apparatus, futuremethods, and different materials.

All methods described herein can be performed in a suitable order unlessotherwise indicated herein or otherwise clearly contradicted by context.The use of any and all examples, or exemplary language (e.g., “suchas”), is intended merely to better illustrate the disclosure and doesnot pose a limitation on the scope of the disclosure unless otherwiseclaimed. No language in the specification should be construed asindicating any non-claimed element as essential to the practice of thedisclosure as used herein.

Terminology used in the present disclosure is intended to include allenvironments and alternate technologies that provide the samefunctionality described herein.

What is claimed is:
 1. A method of forming a coaxial structure, saidcoaxial structure comprising a concentric reference structure and afirst and second through-via formed therein, in an insulativesemiconductor substrate core, said method comprising the steps of:forming a hole in said insulative semiconductor substrate core, saidhole having an inner surface from a first side of said insulativesemiconductor substrate core to a second side of said insulativesemiconductor substrate core; depositing over said inner surface of saidhole in said insulative semiconductor substrate a conductive material toform said concentric reference structure from said first side of saidinsulative semiconductor substrate core to said second side of saidinsulative semiconductor substrate core through said hole; depositing afirst dielectric material in said hole; depositing a second dielectricmaterial on said surface of said first and second sides of saidinsulative semiconductor substrate core; forming said first and secondthrough-via through said second dielectric material on said first andsecond sides of said insulative semiconductor substrate core and withinsaid first dielectric material in said hole.
 2. The method of claim 1wherein said first dielectric material and said second dielectricmaterial are the same dielectric material.
 3. The method of claim 1wherein said first dielectric material and said second dielectricmaterial are different dielectric materials.
 4. The method of claim 1wherein said depositing over said inner surface of said hole aconductive material to form said concentric reference structure is byconductive ink-fill techniques.
 5. The method of claim 1 wherein saidforming of said first and second through-via is by conductive ink-filltechniques.
 6. A method for forming a coaxial structure, said coaxialstructure comprising a concentric reference structure and a first andsecond through via formed therein, in a conductive semiconductorsubstrate core, said method comprising the steps of: forming a firsthole in said conductive semiconductor substrate core, said first holehaving an inner surface from a first side of said conductivesemiconductor substrate core to a second side of said conductivesemiconductor substrate core; depositing a first dielectric material insaid first hole; forming a second hole within said dielectric materialdeposited in said first hole; depositing over said inner surface of saidsecond hole in said conductive semiconductor substrate a conductivematerial to form said concentric reference structure from said firstside of said conductive semiconductor substrate core to said second sideof said conductive semiconductor substrate core through said secondhole; depositing a second dielectric material in said second hole;forming a first and second through vias within said second dielectricmaterial in said second hole.
 7. The method of claim 6 wherein saidfirst dielectric material and said second dielectric material are thesame dielectric material.
 8. The method of claim 6 wherein said firstdielectric material and said second dielectric material are differentdielectric materials.
 9. The method of claim 6 wherein said forming ofsaid concentric reference structure is by conductive ink-filltechniques.
 10. The method of claim 6 wherein said forming of said firstand second through via is by conductive ink-fill techniques.
 11. Apackaging substrate core comprising: a substrate comprising: a firstsurface; a cavity formed into said first surface to a depth less thanthe thickness of said insulating substrate; an active component disposedsaid cavity; and a vertical interconnect module disposed within saidcavity.
 12. The packaging substrate core of claim 11 further comprisingsaid substrate further comprising a first conductive slug moduledisposed within said cavity.
 13. The packaging substrate core of claim11 further comprising said substrate further comprising a verticalinterconnect through a cavity fill material.
 14. The packaging substratecore of claim 13 wherein said vertical interconnect through said cavityfill material is not through said substrate core.